The present invention relates to a semiconductor device and a manufacturing method thereof, particularly to a technology effective when applied to a semiconductor device having an insulated gate biopolar transistor (IGBT).
A variety of technologies for mounting a semiconductor device on a packaging circuit substrate have been proposed.
For example, disclosed in Japanese Unexamined Patent Publication No. Hei 11 (1999)-135533 (Patent Document 1) is an electrode structure of a silicon semiconductor element which is placed over, for example, the surface of a silicon semiconductor, and comprises a first metal layer forming an ohmic contact with the silicon semiconductor and a second metal layer stacked to completely cover the whole exposed surface of the first metal layer, wherein the metal of the second metal layer has higher corrosion resistance to an organic acid and better solder wettability than the metal of the first metal layer.
In Japanese Unexamined Patent Publication No. 2001-271494 (Patent Document 2), disclosed is a semiconductor device characterized by that a surface electrode electrically connected to a semiconductor element has a plurality of conductive layers, of which the conductive layer physically connected to a surface pad electrode is made of a material having good adhesion to the material of the surface pad electrode and that physically connected to a bump is made of a material having good adhesion to the material of the bump.
In Japanese Unexamined Patent Publication No. 2002-134441 (Patent Document 3), disclosed is a manufacturing method of a power semiconductor device, which comprises processing the surface of a substrate, bonding a surface protective tape onto the surface of the substrate prior to deposition of a metal film, which will serve as an electrode, on the backside of the substrate, carrying out first dicing by making a cut line on the substrate along a dicing line from the backside of the substrate, removing the surface protective tape from the substrate surface after deposition of the metal film on the backside, and then carrying out second dicing.
In Japanese Unexamined Patent Publication No. 2003-332271 (Patent Document 4), disclosed is a technology of maintaining the strength of a semiconductor wafer even after the wafer is thinned, which comprises polishing the inner region on the backside of a semiconductor wafer to form a protrusion at the periphery of the backside of the semiconductor wafer, loading the semiconductor wafer on a stage having a surface smaller than the inner region of the semiconductor wafer, supporting the inner region on the backside of the semiconductor wafer by the stage, and cutting a scribe region on the surface of the semiconductor wafer.
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 11 (1999)-135533
[Patent Document 2] Japanese Unexamined Patent Publication No. 2001-271494
[Patent Document 3] Japanese Unexamined Patent Publication No. 2002-134441
[Patent Document 4] Japanese Unexamined Patent Publication No. 2003-332271